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module top;
system_clk #400 clk1(a);
system_clk #200 clk2(b);
system_clk #100 clk3(c);
system_clk #50 clk4(d);
number z1(e,a,b,c,d);
endmodule
module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire la,lb,lc,ld,w1,w2,w3,w4,w5;
not(la,a);
not(lb,b);
not(lc,c);
not(ld,d);
and(w1,a,lb,c,d);
and(w2,a,b,c,ld);
and(w3,la,lb,ld);
and(w4,lb,lc,ld);
and(w5,la,b,lc);
or(e,w1,w2,w3,w4,w5);
endmodule
module system_clock (clk);
parameter PERIOD=100;
output clk; reg clk; initial clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

not and

module top;
wire o,A1,B1;
system_clk #50 clk1(A1);
system_clk #100 clk2(B1);
nanf201 cl(o,A1,B1);
endmodule
module nanf201(o,A1,B1);
input A1,B1;
output o;
nand(o,A1,B1);
specify
specparam
Tpd_0_1=1.13:3.09:7.75,
Tpd_1_0=0.93:2.5:7.34;
(A1=>o)=(Tpd_0_1,Tpd_1_0);
(B1=>o)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(49*period/50)clk=~clk;
#(period-49*period/50)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

OR4_alog

module top;
wire [3:0] x_in;
wire y_out;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
or4_algo cl(y_out,x_in);
endmodule
module or4_algo(y_out,x_in);
input [3:0] x_in;
output y_out;
reg y_out;
integer k;
always @ (x_in)
begin:or_loop
y_out=0;
for(k=0;k<=3;k=k+1)
if(x_in[k]==1)
begin
y_out=1;
disable or_loop;
end
end
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

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